In dynamic random access memory (DRAM) cells, such as the 1T1C cell, the 3T (or 3T1C) gain cell, and the gated diode cells, 0- and 1-data are stored as electric charges in various storage elements, such as a stack capacitor, trench capacitor, transistor gate capacitor, and gated diode. The stored charges can only remain in the storage element for a finite amount of time, as there are leakage paths from the storage node, which holds the charges, to the neighboring nodes. Typical leakage paths are the source-drain path of the write device under sub-threshold leakage, the tunneling leakage through the storage element oxide and the gate oxide of the write device and the read device (as in the case for the 3T, 3T1C, 3T1D and 2T1D cells, for example), and the storage node to silicon body leakage via the junction leakage of the write device.
Traditionally, in order to hold the data for a longer or an indefinite amount of time, the stored charges are periodically “refreshed” in accordance with the “retention time” of the memory. Refreshing of the memory cells is typically carried out by allocating some predetermined time (memory cycles) to reading data from each cell and writing the same data back to the cell. During refreshing of the memory cells, the memory array that contains the cells being refreshed is suspended from the normal read and write operations, thereby reducing the availability of the memory array for normal read and write operations and, hence, potentially reducing the overall system performance. The more often the memory array needs to be refreshed (i.e., the shorter the retention time), the lower the availability of the memory array for normal operations and potentially the lower the overall system performance.
For commodity-type 1T1C DRAM, the refresh interval (which is required to be less than the smallest retention time) for a wordline address is typically 128 ms, with a 20 ns DRAM cycle time. Therefore, in a memory system that has 8 arrays and 512 rows per array (for a total of 4096 words), the refreshing time for the system is 20*4096 ns=80 μs. The percentage of time required for refreshing the memory is 0.06% (80 μs/128000 μs), which is a relatively small penalty for most applications.
The device variability of semiconductor technology has become a major issue as the minimum feature size approaches the physical limits. This leads to the instability of, for example, 6T SRAM cells, which limits the scaling of the cells. Dynamic memory is being considered as a potential alternative for high speed embedded cache in order to attain better density and to address the stability issues facing the 6T SRAM cells (which have been traditionally used in the area). For high speed dynamic cache memory, the refresh interval is smaller (for example, about 10-348 μs) due to the smaller cell retention time associated with the logic-based embedded DRAM technology (with a 2 ns refresh cycle time, for example). Therefore, for example, in a memory system that has 8 arrays and 128 rows per array (for a total of 1024 rows), the refreshing time is 2048 ns (2 ns*1024 rows). Assuming an exemplary refresh interval of 20 μs, the percentage of time required for refreshing the high speed memory is 10% (2048 rows/35200 ns). Assuming a typical L2 cache miss ratio of 5% using conventional 6T SRAM, the exemplary 10% cache utilization for refreshing the dynamic cells will significantly impact the cache performance.
For a given high speed dynamic memory cell with a certain retention time, it would be beneficial to improve the refreshing scheme by hiding the refresh cycles for read operations, write operations, or both, in order to make either the read operation, the write operation, or both operations more highly available. That is, if a refresh cycle were “hidden,” it would not prevent the carrying out of a read or write operation, as the case may be, during the “hidden” refresh.